| 摘要 |
The present invention relates to a clock buffer circuit capable of preventing the generation of an incomplete clock when a buffering function is on or off. According to at least one embodiment of the present invention, a complete clock is generated by outputting a clock when a stable clock is generated and the incomplete clock which is generated in the on of the buffering function is blocked for preset time. [Reference numerals] (300) Buffering unit;(301) Output unit;(302) Delay device;(AA) Enable signal |
