| 摘要 |
A microprocessor capable of operating as both an x86 instruction set architecture (ISA) microprocessor and an Advanced RISC Machines (ARM) ISA microprocessor, the microprocessor comprising: first storage, that stores x86 ISA-specific state of the microprocessor; second storage, that stores ARM ISA-specific state of the microprocessor; and third storage, that stores non-ISA-specific state of the microprocessor wherein, in response to a reset, the microprocessor initializes the first storage to default values specified by the x86 ISA; initializes the second storage to default values specified by the ARM ISA; initalizes the third storage to predetermined values; and begins fetching instructions of a first ISA, wherein the first ISA is the x86 ISA or the ARM ISA and a second ISA is the other ISA, wherein the microprocessor updates at least a portion of the third storage in response to one or more of the first ISA instructions, wherein, in response to a subsequent one of the first ISA instructions that instructs the microprocessor to reset to the second ISA, the microprocessor: refrains from modifying the non-ISA-specific state stored in the third storage; and begins fetching instructions of the second ISA. |
