Interface system, and corresponding integrated circuit and method

摘要

An interface system (10) for interfacing an asynchronous circuit with a synchronous circuit, wherein the synchronous circuit samples, in response to a clock signal (CLK RX), a first data signal (DATA) when a first control signal (REQ) indicates that the first data signal (DATA) contains valid data, and wherein the asynchronous circuit (4) generates a second data signal (ADATA) according to an asynchronous communication protocol. In particular, the system comprises:
- a First-In First-Out memory (18) comprising a plurality of memory locations,
- a control circuit (20) configured for:
a) asynchronously writing (204, 206) the second data signal (ADATA) in the memory (18) when the second data signal (ADATA) indicates the start of a communication, and
b) synchronously reading (200, 202) the second data signal (ADATA') from the memory (18) in response to a clock signal (CLK_RX),
- a conversion circuit (12) configured for decoding, according to a asynchronous communication protocol, the second data signal (ADATA') read from the memory (18) in a decoded data signal, wherein the decoded data signal corresponds to the first data signal (DATA).