发明名称 PLL CIRCUIT
摘要 <p>It has been difficult that conventional PLL circuits have a suppression characteristic of suppressing the phase noise which is free of variation due to temperature and individual difference and stable in a wide frequency band. The present invention provides a PLL circuit which can absorb variation of phase noise characteristic due to temperature and individual difference and has a phase noise suppression characteristic stable in a wide frequency band. The PLL circuit comprises, at the succeeding stage, a first register (6) for storing a first parameter for controlling the loop gain, a first multiplier (7) for multiplying the output of the phase comparator (4) by a first parameter, a second register (12) for storing a second parameter for controlling the response characteristic, a second multiplier (13) for multiplying the output of the first multiplier by a second parameter, and a CPU (20) for setting optimum parameters in the first and second registers depending on the use frequency band, the ambient temperature, and the device individual difference. By controlling the loop gain and the response characteristic to optimum values, a good suppression characteristic in a wide frequency band is achieved.</p>
申请公布号 EP1988634(B1) 申请公布日期 2013.11.27
申请号 EP20070737348 申请日期 2007.02.23
申请人 NIHON DEMPA KOGYO CO., LTD. 发明人 KIMURA, HIROKI;KOBATA, TSUKASA;KITAYAMA, YASUO;ONISHI, NAOKI
分类号 H03L7/107;H03L7/093;H03L7/18 主分类号 H03L7/107
代理机构 代理人
主权项
地址