发明名称 Computer system
摘要 <p>A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.</p>
申请公布号 EP2386960(B1) 申请公布日期 2013.11.27
申请号 EP20110164649 申请日期 2011.05.03
申请人 RENESAS ELECTRONICS CORPORATION 发明人 YAMADA HIROMICHI;SHIMAMURA, KOTARO;KANEKAWA, NOBUYASU;ISHIGURO, YUICHI
分类号 G06F13/26 主分类号 G06F13/26
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