| 摘要 |
Some of the embodiments of the present disclosure provide a D type flip-flop, comprising a first sampling module configured to sample an input signal while the input signal is at a low logical value; a second sampling module configured to sample the input signal while the input signal is at a high logical value; and a latch configured to logically generate an output signal responsively to the sampling of the input signal by the first sampling module and by the second sampling module. Other embodiments are also described and claimed.
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