发明名称 logic circuit for prevention DPA using of Hamming Weight Model, and smart card included it
摘要 PURPOSE: A power analysis attack prevention logic circuit using a Hamming weight model and a smart card including the same are provided to fundamentally prevent power analysis attack. CONSTITUTION: A power analysis attack prevention logic circuit installs a logic circuit(100) and an FET(Field-Effect Transistor) device(210). The logic circuit includes a logic gate(110). The FET device has the same characteristic as the logic gate and is installed in an output end(130) of the logic gate. The power analysis attack prevention logic circuit maintains the total current of the logic circuit constant.
申请公布号 KR101332376(B1) 申请公布日期 2013.11.26
申请号 KR20110112402 申请日期 2011.10.31
申请人 发明人
分类号 G06F7/00;H03K19/20 主分类号 G06F7/00
代理机构 代理人
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