发明名称 Apparatuses and methods including memory array and data line architecture
摘要 Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.
申请公布号 US8593869(B2) 申请公布日期 2013.11.26
申请号 US201113192248 申请日期 2011.07.27
申请人 TANZAWA TORU;MICRON TECHNOLOGY, INC. 发明人 TANZAWA TORU
分类号 G11C16/00 主分类号 G11C16/00
代理机构 代理人
主权项
地址