发明名称 Semiconductor package and method for manufacturing the same
摘要 <p>PURPOSE: A semiconductor package and a method for manufacturing the same are provided to minimize warpage due to the difference of thermal expansion coefficient between a chip and a substrate by laminating a base wafer functioning as an interposer. CONSTITUTION: A through silicon via (12) is formed in the upper part of a base wafer (10). A non-conductive adhesive member (20) for an underfill is sprayed to the base wafer. A semiconductor chip (14) is attached to the upper surface of the through silicon via and electrically connected to the upper surface. A first conductive connector (18) is bonded to the bonding pad on the bottom surface of the semiconductor chip. A molding compound resin (22) encapsulates the semiconductor chip laminated by the first conductive connector.</p>
申请公布号 KR101332857(B1) 申请公布日期 2013.11.22
申请号 KR20110139674 申请日期 2011.12.22
申请人 发明人
分类号 H01L23/12;H01L23/48 主分类号 H01L23/12
代理机构 代理人
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