发明名称 DYNAMIC CLOCK PHASE CONTROL ARCHITECTURE FOR FREQUENCY SYNTHESIS
摘要 Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.
申请公布号 US2013307602(A1) 申请公布日期 2013.11.21
申请号 US201313895849 申请日期 2013.05.16
申请人 MACTAGGART IAIN ROSS 发明人 MACTAGGART IAIN ROSS
分类号 H03L7/16;H03K5/13 主分类号 H03L7/16
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