发明名称 METHOD, SYSTEM AND ARCHITECTURE FOR TESTING RESISTIVE TYPE MEMORY
摘要 PROBLEM TO BE SOLVED: To provide a method for massive parallel screening for testing resistive type memories, and a method for retention testing, functional testing, and fast test initialization.SOLUTION: The method includes the steps of: coupling bit lines of a plurality of resistive type memory cells to a current driver; holding a VCP pad or an external pin at a test write voltage level for a period of time associated with a test write pulse width while the current driver provides the bit lines with a ground voltage level; providing, in parallel, a first write test current in a first direction for driving the memory cells to write data; holding the VCP pad or the external pin at the ground voltage level for a period of time associated with the test write pulse width while the current driver provides the bit lines with the test write voltage level; and providing, in parallel, a second write test current in a second direction opposite to the first direction for driving the memory cells to write data.
申请公布号 JP2013235646(A) 申请公布日期 2013.11.21
申请号 JP20130098326 申请日期 2013.05.08
申请人 SAMSUNG ELECTRONICS CO LTD 发明人 ADRIAN E ONG
分类号 G11C29/12;G11C11/15;G11C13/00 主分类号 G11C29/12
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