| 摘要 |
An integrated circuit comprises a memory or other circuit core having an input interface and an output interface, scan circuitry comprising at least one scan chain having a plurality of scan cells, and additional circuitry associated with at least one of the input interface and the output interface and testable utilizing said at least one scan chain. The scan circuitry further comprises a scan controller configured to control signal values applied to one or more signal lines of the input interface in conjunction with testing of the additional circuitry utilizing said at least one scan chain. For example, the scan controller may control signal values applied to respective address input and write enable signal lines in a manner that ensures that data written to a memory in a write operation of a given memory cycle can be read from the memory in a read operation of a subsequent memory cycle.
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