发明名称 |
EFFICIENT LOCKING OF MEMORY PAGES |
摘要 |
An apparatus is described that contains a processing core comprising a CPU core and at least one accelerator coupled to the CPU core. The CPU core comprises a pipeline having a translation look aside buffer. The CPU core comprising logic circuitry to set a lock bit in attribute data of an entry within the translation look-aside buffer entry to lock a page of memory reserved for the accelerator.
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申请公布号 |
US2013311738(A1) |
申请公布日期 |
2013.11.21 |
申请号 |
US201213996438 |
申请日期 |
2012.03.30 |
申请人 |
JIANG XIAOWEI;GAO HONGLIANG;FANG ZHEN;MAKINENI SRIHARI;IYER RAVISHANKAR |
发明人 |
JIANG XIAOWEI;GAO HONGLIANG;FANG ZHEN;MAKINENI SRIHARI;IYER RAVISHANKAR |
分类号 |
G06F12/14 |
主分类号 |
G06F12/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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