发明名称 INSTRUCTION SEQUENCE BUFFER TO ENHANCE BRANCH PREDICTION EFFICIENCY
摘要 A method for outputting alternative instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor. A frequently miss-predicted branch instruction is identified, wherein the predicted outcome of the branch instruction is frequently wrong. An alternative instruction sequence for the branch instruction target is stored into a buffer. On a subsequent hit to the branch instruction where the predicted outcome of the branch instruction was wrong, the alternative instruction sequence is output from the buffer.
申请公布号 US2013311759(A1) 申请公布日期 2013.11.21
申请号 US201113879365 申请日期 2011.10.12
申请人 ABDALLAH MOHAMMAD;SOFT MACHINES, INC. 发明人 ABDALLAH MOHAMMAD
分类号 G06F9/38 主分类号 G06F9/38
代理机构 代理人
主权项
地址