VIRTUAL FAIL ADDRESS GENERATION SYSTEM, REDUNDANCY ANALYSIS SIMULATION SYSTEM, AND METHOD THEREOF

摘要

A fault distribution generation system is provided. The fault distribution generation system comprises: a fail address mapping module which receives a fail bit map representing failures included in a semiconductor device as a plurality of pixels having a plurality of different failure levels and fail addresses for the failures included in the semiconductor device, and maps the fail addresses to each pixel of the fail bit map; a fault pattern analyzing module which receives information on each pixel to which the fail addresses are mapped from the fail address mapping module, analyzes the received information, and classifies the failures included in each pixel into predetermined fault patterns; and a fault distribution estimating module which estimates an occurrence probability distribution of the fault patterns according to the failure levels based on results of the classification of the fault pattern analyzing module.