| 摘要 |
PROBLEM TO BE SOLVED: To prevent TAT (Turn Around Time) of designing from being longer. SOLUTION: An operation synthesizing device 10 constitutes a logical circuit including a plurality of instances associated to each of a plurality of hardware resources for achieving a predetermined operation by hardware from operation description describing the predetermined operation, and creates RTL (Register Transfer Level) description as input to logical synthesis including a signal name of each of a plurality of signals input/output in the logical circuit from the logical circuit. The device includes: a first signal name specifying part which specifies the signal name of the signal indicating the determination result according to prescribed determination conditions among the plurality of signal names included in the created RTL description; and an indication description creating part which creates description for preventing the signal whose signal name is specified by the first signal name specifying part as description of the logical synthesis together with the created RTL description from being logically compressed in the logical synthesis. COPYRIGHT: (C)2011,JPO&INPIT |
