| 摘要 |
An isolation transistor having a grounded gate is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory device is a DRAM. In another embodiment, the memory device is a 4.5F2 DRAM cell. |
