发明名称 Verifying correctness of processor transactions
摘要 An operation of a processor in respect to transactions is checked by simulating an execution of a test program, and updating a transaction order graph to identify a cycle. The graph is updated based on a value read during an execution of a first transaction and a second transaction that is the configured to set the memory with the read value. The test program comprises information useful for identifying the second transaction.
申请公布号 US8589734(B2) 申请公布日期 2013.11.19
申请号 US20100843068 申请日期 2010.08.26
申请人 ADIR ALLON;LUDDEN JOHN MARTIN;ZIV AVI;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 ADIR ALLON;LUDDEN JOHN MARTIN;ZIV AVI
分类号 G06F11/00 主分类号 G06F11/00
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