发明名称 High frequency switching circuit reducing power consumption and method of controlling the same
摘要 There is provided a high frequency switching circuit reducing power consumption at the time of signal reception and signal transmission. The high frequency switching circuit includes a pulse generation unit generating a clock selecting pulse signal having a predetermined active period; a clock selection unit selecting a reference clock signal when the clock selecting pulse signal is in an active state and selecting a low-speed clock signal having a frequency lower than that of the reference clock signal when the clock selecting pulse signal is not in an active state; a voltage down unit accumulating negative charges in a capacitor to generate predetermined negative voltage; and a switching unit including at least one switch holding a turned-off state by being applied with the predetermined negative voltage.
申请公布号 US8587363(B2) 申请公布日期 2013.11.19
申请号 US201213355306 申请日期 2012.01.20
申请人 OTOBE EIICHIRO;SAMSUNG ELECTRO-MECHANICS CO., LTD. 发明人 OTOBE EIICHIRO
分类号 H03K17/687 主分类号 H03K17/687
代理机构 代理人
主权项
地址