MEMORY DEVICE PERFORMING MULTIPLE CORE ACCESSES WITH BANK GROUP

摘要

Disclosed is a memory device for performing multi-core access in bank groups. The burst length of the memory device is b which is an integer and is bigger than two. The memory device performs core access k times per command and receives the command. The k value is more than two and less than the b. The memory device comprises a memory cell array; a plurality of bank group control units; and a multiplexer. The memory cell array comprises a plurality of bank groups. The bank group control units are positioned in each bank group The bank group control units generate a multiplexer control signal which selects a part of reading data of a corresponding bank group. The multiplexer successively outputs the reading data of the bank groups according to the multiplexer control signal received from the bank group control units. Each data included in the output data of the multiplexer has the same time length. [Reference numerals] (170) First bank group control unit;(180) Second bank group control unit