发明名称 |
Speeding Up Younger Store Instruction Execution after a Sync Instruction |
摘要 |
Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.
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申请公布号 |
US2013305022(A1) |
申请公布日期 |
2013.11.14 |
申请号 |
US201213470386 |
申请日期 |
2012.05.14 |
申请人 |
EISEN SUSAN E.;LE HUNG Q.;LLOYD BRYAN J.;NGUYEN DUNG Q.;RAY DAVID S.;STOLT BENJAMIN W.;TUNG SHIH-HSIUNG S.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
EISEN SUSAN E.;LE HUNG Q.;LLOYD BRYAN J.;NGUYEN DUNG Q.;RAY DAVID S.;STOLT BENJAMIN W.;TUNG SHIH-HSIUNG S. |
分类号 |
G06F9/312 |
主分类号 |
G06F9/312 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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