发明名称 |
INPUT JITTER FILTER FOR A PHASE-LOCKED LOOP (PLL) |
摘要 |
An input jitter filter for a phase-locked loop and methods of use are provided. The method includes generating a masking zone around falling edges of a feedback signal. The method also includes determining that one or more outputs of a phase detector fall within the masking zone. The method further includes ignoring input clock noise when the one or more outputs of the phase detector fall within the masking zone. |
申请公布号 |
US2013300469(A1) |
申请公布日期 |
2013.11.14 |
申请号 |
US201213468268 |
申请日期 |
2012.05.10 |
申请人 |
KELKAR RAM;PAKBAZ FARAYDON;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
KELKAR RAM;PAKBAZ FARAYDON |
分类号 |
H03L7/085;H03L7/08 |
主分类号 |
H03L7/085 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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