摘要 |
An amplification stage comprising: a combiner to generate a sum input signal by combining a voltage signal with a DC bias voltage; a subtractor to generate a difference input signal by subtracting the voltage signal from the DC bias voltage; a first transistor for generating a first part of an amplifier output signal from the sum input signal; a second transistor for generating a second part of an amplifier output signal from the difference input signal; a combiner for combining the first and second parts of the amplifier output signal; a sensing circuit arranged to sense a current flowing in each of the first and second transistors; a control circuit arranged to determine the quiescent current of the first and second transistors in dependence on the sensed currents; and an adjustment circuit arranged to adjust the DC bias voltage in order to minimise variation in the quiescent current. |