| 摘要 |
<p>A delay element 3 delays an output signal Dt from an arithmetic circuit 1 and outputs a delayed signal Dd. An XOR element 4 compares the output signal Dt with the delayed signal Dd, and outputs an XORout signal with the signal value "0" when the signals match each other, and outputs an XORout signal with the signal value "1" when the signals do not match each other. In a flip-flop 61, when the signal value of the XORout signal at the rise of a clock of a clock signal CK is "0", the output signal Dt is output from a flip-flop 6, and when the signal value of the XORout signal at the rise of the clock becomes "1" even once, a fixed value of the signal value "0" continues to be output.</p> |
