发明名称 |
Turbo parallel concatenated convolutional code implementation on multiple-issue processor cores |
摘要 |
An iterative PCCC encoder includes a first delay line operative to receive at least one input data sample and to generate a plurality of delayed samples as a function of the input data sample. The encoder further includes a second delay line including a plurality of delay elements connected in a series configuration. An input of a first one of the delay elements is adapted to receive a sum of first and second signals, the first signal generated as a sum of the input data sample and at least one of the delayed samples, and the second signal generated as an output of a single one of the delay elements. A third delay line in the encoder is operative to generate an output data sample as a function of the sum of the first and second signals and a delayed version of the sum of the first and second signals.
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申请公布号 |
US8583993(B2) |
申请公布日期 |
2013.11.12 |
申请号 |
US201113162734 |
申请日期 |
2011.06.17 |
申请人 |
KALFON SHAI;RABINOVITCH ALEXANDER;LSI CORPORATION |
发明人 |
KALFON SHAI;RABINOVITCH ALEXANDER |
分类号 |
H03M13/00 |
主分类号 |
H03M13/00 |
代理机构 |
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