发明名称 ALL DIGITAL PHASE LOCKED LOOP AND METHOD OF CONTROLLING PHASE LOCKING FOR ALL DIGITAL
摘要 There are provided an all digital phase locked loop and a method of controlling the same. The all digital phase locked loop includes a phase comparator comparing phases of a target signal having a reference frequency and a digital oscillation feedback signal having a feedback frequency; a virtual value controller controlling a preset initial virtual value according to a phase comparison result from the phase comparator to generate an adjusted virtual value when the reference frequency is a frequency included between two preset lower and higher digital codes; a random number generator generating a random number within a range of a plurality of virtual values; a comparator generating digital codes; and a digitally controlled oscillator generating an oscillation signal according to the digital codes from the comparator.
申请公布号 KR101328372(B1) 申请公布日期 2013.11.11
申请号 KR20120019677 申请日期 2012.02.27
申请人 发明人
分类号 G06F7/58;H03L7/085 主分类号 G06F7/58
代理机构 代理人
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