REDUCING POWER IN SRAM USING SUPPLY VOLTAGE CONTROL

摘要

An embodiment of the invention provides a method for decreasing power in a static random access memory (SRAM). A first voltage is applied between latch sourcing and latch sinking supply lines for columns of memory cells that are column addressed during a read cycle. A second voltage is applied between latch sourcing and latch sinking supply lines for columns of memory cells that are not column addressed during a read cycle. Because the second voltage is less than the first voltage, power in the SRAM is reduced. In this embodiment, a memory cell in the SRAM includes at least one read buffer and a latch connected between the latch sourcing and latch sinking supply lines.