发明名称 |
Method, apparatus and computer program for solving control bits of butterfly networks |
摘要 |
Control bits for switches of a butterfly network are directly solved iteratively for each successive functional column of switches to route data values in parallel according to a multiple access scheme through the butterfly network to memory spaces. A memory space address and appended bus index leading into the butterfly network are generated. A linear order bus index and a physical address are determined for a switch having an unsolved control bit. The solved control bits are applied to solve control bits to a next functional column in a linear and an interleaved order by starting from the bus index and physical address. The linear order is moved to the interleaved order by a reduced turbo de-interleaver and the interleaved order is moved to the linear order by a reduced turbo interleaver until solving a sequence of control bits related to the start bus index and the start physical address.
|
申请公布号 |
GB2492249(B) |
申请公布日期 |
2013.11.06 |
申请号 |
GB20120011610 |
申请日期 |
2012.06.29 |
申请人 |
RENESAS MOBILE CORPORATION |
发明人 |
ESKO JUHANI NIEMINEN |
分类号 |
H03M13/29;H03M13/27 |
主分类号 |
H03M13/29 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|