A DIGITAL DELAY-LOCKED LOOP USING A PHASE-INVERSION ALGORITHM AND METHOD FOR CONTROLLING THE SAME

摘要

The present invention relates to a digital delay-locked loop circuit using a phase-inversion lock algorithm and a method for controlling the same. The digital delay-locked loop circuit comprises: a phase-inversion lock control circuit which controls whether to use the phase-inversion lock algorithm by detecting a phase difference between an input clock and an output clock; an inverter which outputs an inverted input clock after inverting the input clock; a multiplexer which receives the input clock and the inverted input clock output from the inverter as an input signal, and outputs the input clock or the inverted input clock according to a control signal of the phase-inversion lock control circuit; and a phase-synchronization unit which is connected to an output terminal of the multiplexer, and performs phase-synchronization after receiving an output signal of the multiplexer. [Reference numerals] (110) Reversal locking control circuit;(140) Three step digital control delay line (TDCDL);(141) 1'st DCDL (delay resolution = �t1);(142) 2'st DCDL (delay resolution = �t2 = �t1/2);(143) FDL (delay resolution = �t3 = �t2/16);(150) Phase detector;(160) 9-bit variable successive approximate register;(170) 4-to-16 thermometer decoder;(180) Successive approximate register control circuit