发明名称 Memory module including memory buffer and memory system having the same
摘要 A memory buffer selecting between a parallel test mode and a mode register control mode, and a memory module and memory system having the memory buffer are disclosed. The memory buffer includes a control circuit and a mode selecting circuit. The control circuit generates a mode control signal based on a first chip selecting signal, a second chip selecting signal, a row address signal, a column address signal, and a write enable signal. The mode selecting circuit selects one of a parallel test mode and a mode register control mode in response to the mode control signal.
申请公布号 US8576637(B2) 申请公布日期 2013.11.05
申请号 US20100959504 申请日期 2010.12.03
申请人 JANG SOON-DEOK;KIM SEOK-IL;SEO SEUNG-JIN;HAN YOU-KEUN;SAMSUNG ELECTRONICS CO., LTD. 发明人 JANG SOON-DEOK;KIM SEOK-IL;SEO SEUNG-JIN;HAN YOU-KEUN
分类号 G11C7/10 主分类号 G11C7/10
代理机构 代理人
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