发明名称 |
Method and integrated circuit for increasing the immunity to interference |
摘要 |
Disclosed is a method of improving the immunity to interference of an integrated circuit (16) having error signals transferred between a microprocessor chip or multiple processor muC (1) and an additional component (2). For the transfer, a minimum pulse length that is independent of the clock frequency of the microprocessor or the microprocessors is defined, starting from which a signal on an error line having a defined pulse length is interpreted as an error. Also disclosed is an integrated circuit, which is designed so that the above method is implemented. The circuit has a microprocessor chip or multiple processor microcontroller (1) or microprocessor module and an additional component (2) having separately arranged power elements. The circuit also has pulse extending devices and/or signal delaying devices for the output of error pulses (6, 6') one after the other through at least one error line (3, 4).
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申请公布号 |
US8578258(B2) |
申请公布日期 |
2013.11.05 |
申请号 |
US20050590087 |
申请日期 |
2005.02.17 |
申请人 |
FEY WOLFGANG;HEINZ MICHA;TRASKOV ADRIAN;MICHEL FRANK;CONTINENTAL TEVES AG & CO., OHG |
发明人 |
FEY WOLFGANG;HEINZ MICHA;TRASKOV ADRIAN;MICHEL FRANK |
分类号 |
G06F11/00;G06F11/07;G06F11/16;G06F11/267 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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