| 摘要 |
Power-saving and area-efficient BCH coding systems are provided that employ hybrid decoder architectures. The BCH decoder architectures comprise both special-purpose hardware and firmware, thereby taking advantage of both the speed of special-purpose hardware and the energy-efficiency of firmware. In particular, the error correction capabilities of the BCH decoders provided herein are split between a hardware component designed to correct a single error and a firmware component designed to correct the remaining errors. In this manner, firmware operation is bypassed in situations where only one error is present and the complexity of the necessary hardware is significantly reduced.
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