发明名称 |
PLL circuit, error correcting method for the same, and communication apparatus including the same |
摘要 |
A PLL circuit includes: the number-of-accumulated clocks detecting portion detecting the number of accumulated clocks of an oscillation circuit as a digital value; a periodicity detecting portion detecting periodicity of a digital value of a fractional portion of the number of accumulated clocks of the oscillation circuit with a first reference clock as a reference; a corrected value calculating portion calculating a corrected value; and an adding portion adding the corrected value to the fractional portion of the number of accumulated clocks with the first reference clock from the starting points of the periods of the periodicity.
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申请公布号 |
US8575980(B2) |
申请公布日期 |
2013.11.05 |
申请号 |
US201113282841 |
申请日期 |
2011.10.27 |
申请人 |
TSUDA SHINICHIRO;SONY CORPORATION |
发明人 |
TSUDA SHINICHIRO |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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