SCAN TEST CIRCUIT, TEST PATTERN GENERATION CONTROL CIRCUIT, AND SCAN TEST CONTROL METHOD

摘要

PROBLEM TO BE SOLVED: To improve the delay failure detection rate without increasing an area overhead.SOLUTION: A scan test circuit includes: scan flip-flops 3 to 8 constituting a clock domain which operates by an identical clock in a semiconductor integrated circuit that has a target for a delay failure test; a test pattern generation method control unit (a scan flip-flop 1) that is provided with the same clock as the one provided for scan flip-flops 1 to 8 and selects one of a skew load method and a broadside method as a test pattern generation method; a scan enable signal output unit (an OR gate 31) that outputs a first scan enable signal, which is determined on the basis of the test pattern generation method, to the scan flip-flops 3 to 8.