| 摘要 |
A display device comprises a display panel in which data lines and gate lines cross each other, a timing controller which outputs a single gate pulse modulation control signal (FLK signal) and I-phase (where I is an integer equal to or more than 2) gate shift clocks which are sequentially delayed, an FLK dividing circuit which divides the single FLK signal to output J (where J is an integer equal to or more than 2 and smaller than I) FLK signals, a data driving circuit which converts digital video data into data voltages to supply the data voltages for the data lines, and a gate driving circuit which generates gate pulses by level-shifting voltages of the gate shift clocks, to modulate falling edge voltages of the gate pulses in response to the divided FLK signals, and to sequentially supply the modulated gate pulses for the gate lines. |
