发明名称 INTERPOLATION CIRCUIT AND RECEIVING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To suppress a circuit scale.SOLUTION: An interpolation circuit includes: a generating circuit that generates interpolation data from a plurality of data of input data inputted in time series; a first ADC 40 that converts the interpolation data of a data point into digital data; and a second ADC 42 that converts the interpolation data of a change point into the digital data and has a quantization bit number smaller than that of the first ADC.
申请公布号 JP2013225821(A) 申请公布日期 2013.10.31
申请号 JP20120098205 申请日期 2012.04.23
申请人 FUJITSU LTD 发明人 SHIBAZAKI TAKAYUKI
分类号 H04L25/03 主分类号 H04L25/03
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