发明名称 SEMICONDUCTOR LAYOUT DEVICE, SEMICONDUCTOR LAYOUT METHOD, AND SEMICONDUCTOR LAYOUT PROGRAM
摘要 PROBLEM TO BE SOLVED: To solve the problem of electromigration so as to perform layout design which achieves high integration.SOLUTION: A frequency analysis unit 802 generates wiring frequency data, in which an operation frequency of each of wirings included in a semiconductor integrated circuit is described, on the basis of design information of the semiconductor integrated circuit that is a layout target. A wiring unit 810 determines an arrangement position of one wiring included in the semiconductor integrated circuit according to the design information and arranges one or more single vias on the wiring; and performs an electromigration check for the wiring on the basis of the wiring frequency data and design information. The wiring unit 810 performs conversion processing that converts at least part of the single vias on the wiring into redundant vias on the basis of a check result; adjusts the arrangement position of the wiring; and reflects it in the layout of a semiconductor integrated device. The wiring unit 810 performs the above-described processing for all the wirings.
申请公布号 JP2013225194(A) 申请公布日期 2013.10.31
申请号 JP20120096486 申请日期 2012.04.20
申请人 RENESAS ELECTRONICS CORP 发明人 URA TAKAYORI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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