发明名称 MOUNTING METHOD FOR SEMICONDUCTOR ELEMENT
摘要 PROBLEM TO BE SOLVED: To provide a mounting method for a semiconductor element in which shorting between adjoining connection pads is prevented for good electrical connection between a wiring board and a semiconductor element.SOLUTION: In a mounting method for a semiconductor element S, the semiconductor element S having a first thermal expansion coefficient in the direction along a connection surface C in which a plurality of electrode terminals T are disposed, is mounted, by performing a reflow processing so that an electrode terminal T is jointed to a connection pad 2 through a solder bump 4, on a wiring board 10 having a second thermal expansion coefficient which is larger than the first thermal expansion coefficient in the direction along a mounting surface 1a in which a plurality of connection pads 2 connected to the electrode terminal T are disposed. An array pitch P1 of the electrode terminal T at a normal temperature before the reflow processing, an array pitch P2 of the connection pad 2, and an array pitch P3 of the solder bump 4 are set in such a manner as the array pitch P2 of the connection pad 2 is smaller than the array pitch P1 of the electrode terminal T, and the array pitch P1 of the electrode terminal T matches the array pitch P3 of the solder bump 4.
申请公布号 JP2013225611(A) 申请公布日期 2013.10.31
申请号 JP20120097596 申请日期 2012.04.23
申请人 KYOCER SLC TECHNOLOGIES CORP 发明人 MIZUMOTO SHOGO;SHISHIDO ITSURO
分类号 H01L21/60 主分类号 H01L21/60
代理机构 代理人
主权项
地址