发明名称 |
ANALOG-TO-DIGITAL CONVERTER TIMING CIRCUITS |
摘要 |
<p>An analog-to-digital converter timing circuit disclosed herein uses a clock generation circuit that makes the analog-to-digital converter insensitive to input clock duty cycle. Minimum clock jitter is added to the clock signal while propagating through the disclosed circuit. A method and system are also disclosed to clock an interleaved pipelined ADC such that the operation is insensitive to input clock duty cycle and such that the clock jitter on the sampling clock edges is minimized.</p> |
申请公布号 |
EP2255262(B1) |
申请公布日期 |
2013.10.30 |
申请号 |
EP20080870833 |
申请日期 |
2008.12.10 |
申请人 |
HITTITE MICROWAVE NORWAY AS |
发明人 |
HERNES, BJORNAR;TELSTO, FRODE;ANDERSEN, TERJE, NORTVEDT |
分类号 |
H03K5/151;G06F1/04;H03K5/156 |
主分类号 |
H03K5/151 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|