发明名称 INFORMATION PROCESSING SYSTEM
摘要 <p>Access contention for a shared resource (106) is resolved while suppressing power consumption in an information processing system (100). A bus controller (108) using a cache miss detecting unit (119), detects first information that indicates with respect to a CPU (101) and a CPU (102), a cache hit or a cache miss. The bus controller (108) using a high-speed I/O detecting unit (120), detects second information that indicates an activated state or a non-activated state of a DMA controller (103) and a DMA controller (104). The bus controller (108) using a generating unit (123), generates a setting signal based on the first information and the second information.</p>
申请公布号 EP2657847(A1) 申请公布日期 2013.10.30
申请号 EP20100859818 申请日期 2010.11.15
申请人 FUJITSU LIMITED 发明人 YAMASHITA, KOICHIRO;YAMAUCHI, HIROMASA;SUZUKI, TAKAHISA;KURIHARA, KOJI;HAYAKAWA, FUMIHIKO
分类号 G06F12/08;G06F1/32;G06F13/36 主分类号 G06F12/08
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