| 摘要 |
PURPOSE: A prescaler, a dual mode prescaler, and a phase locked loop circuit using the same are provided to perform frequency demultiply as sequentially repeating the states of flip-flops. CONSTITUTION: A prescaler generating an output clock signal by performing the N demultiply of an input clock signal includes first to K-th flip-flops (110-1 to 110-K), and a NOR gate (120). The first to K-th flip-flops sequentially and serially connect an input terminal and an output terminal, and respectively apply the input clock signal. The NOR gate is connected to the output terminal of the first to R-th flip-flops, and performs the NOR operation of applied signals. The NOR gate applies the operated signal to the input terminal of the K-th flip-flop. [Reference numerals] (AA) Input clock signal; (BB) Output clock signal |
