发明名称 |
Address multiplexing in pseudo-dual port memory |
摘要 |
A pseudo-dual port memory address multiplexing system includes a control circuit operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit monitors a read operation and generates a switching signal when the read operation is determined to be complete. A multiplexer is responsive to the switching signal for selectively providing a read address and a write address to a memory address unit at the proper time.
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申请公布号 |
US8570818(B2) |
申请公布日期 |
2013.10.29 |
申请号 |
US20100814682 |
申请日期 |
2010.06.14 |
申请人 |
JUNG CHANG HO;ZHONG CHENG;QUALCOMM INCORPORATED |
发明人 |
JUNG CHANG HO;ZHONG CHENG |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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