发明名称 |
Accurate parasitic capacitance extraction for ultra large scale integrated circuits |
摘要 |
A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
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申请公布号 |
US8572537(B2) |
申请公布日期 |
2013.10.29 |
申请号 |
US201213527096 |
申请日期 |
2012.06.19 |
申请人 |
SU KE-YING;HO CHIA-MING;CHANG GWAN-SIN;CHEN CHIEN-WEN;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
SU KE-YING;HO CHIA-MING;CHANG GWAN-SIN;CHEN CHIEN-WEN |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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