发明名称 Memory device and fabricating method thereof
摘要 According to one embodiment, a memory device includes first interconnects, second interconnects, and a first memory cell. The first memory cell is located in an intersection of one of the first interconnects and one of the second interconnects. The first memory cell includes a first multilayer structure and a first variable resistance layer, the first multilayer structure including a first electrode, a first selector, and a first insulator which are stacked. The first selector and the first variable resistance layer are electrically connected in series between the one of the first interconnect and the one of the second interconnect. The first variable resistance layer is formed on a portion of a side surface of the first insulator to cover the portion without covering a residual portion.
申请公布号 US8570786(B2) 申请公布日期 2013.10.29
申请号 US201113177857 申请日期 2011.07.07
申请人 MUROOKA KENICHI;KABUSHIKI KAISHA TOSHIBA 发明人 MUROOKA KENICHI
分类号 G11C11/00 主分类号 G11C11/00
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