发明名称 Semiconductor memory and semiconductor memory test method
摘要 According to the embodiments, a read circuit is connected to the other end of the bit line for reading out data from read data storing memory cells and test data storing memory cells via the bit line, and a read control circuit makes data to be read out from the test data storing memory cells when testing the bit line and makes data to be read out from the read data storing memory cells when reading out the read data.
申请公布号 US8570822(B2) 申请公布日期 2013.10.29
申请号 US20100978775 申请日期 2010.12.27
申请人 HAMA KAORU;KABUSHIKI KAISHA TOSHIBA 发明人 HAMA KAORU
分类号 G11C7/00 主分类号 G11C7/00
代理机构 代理人
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