发明名称 |
Clock gating cell circuit |
摘要 |
A clock gate includes a first Muller gate that receives at its inputs a clock signal and an enable signal. The output of the first Muller gate is applied, with a delayed version of the clock signal, to a second Muller gate. A logic circuit operates to logically combine the output of the second Muller gate with a delayed version of the clock signal. The output of the logic circuit provides a gated clock output. |
申请公布号 |
US8570069(B2) |
申请公布日期 |
2013.10.29 |
申请号 |
US201213450618 |
申请日期 |
2012.04.19 |
申请人 |
ZID MOUNIR;SCANDURRA ALBERTO;STMICROELECTRONICS S.A.;STMICROELECTRONICS S.R.L. |
发明人 |
ZID MOUNIR;SCANDURRA ALBERTO |
分类号 |
H03K19/096;H04L27/08 |
主分类号 |
H03K19/096 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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