发明名称 TESTING APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT, TEST METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND TEST PROGRAM FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a logic verification method, a verification circuit information extraction program, and a verification circuit modification apparatus, which allow a verification circuit to be applied for both a logic simulator and a format verification tool that support different languages so as to perform efficient testing.SOLUTION: A testing apparatus includes: a verification circuit information extraction unit that extracts verification circuit information from a first verification circuit that is a reuse source; and a verification circuit conversion unit that generates a second verification circuit in a programming language that is specified by using the extracted verification circuit information.
申请公布号 JP2013222365(A) 申请公布日期 2013.10.28
申请号 JP20120094456 申请日期 2012.04.18
申请人 LAPIS SEMICONDUCTOR CO LTD 发明人 SUGANO NAOKI
分类号 G06F17/50 主分类号 G06F17/50
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