| 摘要 |
<p>A gate driver circuit and a display. The gate driver circuit comprises multiple cascaded shift registers. Each shift register comprises: a signal input circuit (1), a signal output circuit (2), an upward pulling circuit (3), a reset circuit (4) and a downward pulling circuit (5). The signal input circuit (1), the signal output circuit (2), the upward pulling circuit (3) and the reset circuit (4) are converged to form a first node PU, and a control end of the downward pulling circuit (5) is a second node PD. An auxiliary transistor (M0) is further provided between two adjacent shift registers, a gate of the auxiliary transistor (M0) is connected with the second node PD of the shift register in the Nth line, a source of the auxiliary transistor (M0) is connected with the first node PU of the shift register in the (N+1)th line, and a drain of the auxiliary transistor (M0) is connected with a signal output end of a signal output circuit of the shift register in the (N+1)th line. The gate driver circuit has low power consumption and a long service life.</p> |
