发明名称 FAULT LOCATION DIAGNOSIS DEVICE, FAULT LOCATION DIAGNOSIS METHOD, AND PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide a fault location diagnosis device which extracts a fault classified as a systematic fault from a test result of a semiconductor integrated circuit that is determined to be defective, thereby facilitating feedback to a manufacturing process.SOLUTION: A fault location diagnosis device includes: a layout characteristic retrieval area calculation unit that calculates a plurality of layout characteristic retrieval areas having each of a plurality of single fault, which are included in multiple faults, as a base point; a layout characteristic extraction unit that extracts a predetermined characteristic as a layout characteristic from constituents that are included in the plurality of layout characteristic retrieval areas; and a fault type determination unit that determines that a systematic fault exists in a semiconductor integrated circuit under test if a layout characteristic common to the plurality of layout characteristic retrieval areas exists.
申请公布号 JP2013217750(A) 申请公布日期 2013.10.24
申请号 JP20120088145 申请日期 2012.04.09
申请人 RENESAS ELECTRONICS CORP 发明人 NIKAIDO MASATO
分类号 G01R31/28 主分类号 G01R31/28
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