| 摘要 |
PROBLEM TO BE SOLVED: To comprehensively determine the presence/absence of a fear that stationary penetration current from a power source to the ground is generated regardless of the input state or input pattern of simulation in an LSI circuit including a logical gate and an FET.SOLUTION: In an input net list including a logical gate and an FET, penetrating condition functions expressing the ON/OFF of the FET disposed on a path going from the power source to the ground or a path going from the output of the logical gate to the power source or the ground with a Boolean expression are extracted. A penetrating condition determination Boolean expression of a logic circuit giving an input to the penetrating condition functions is extracted, and the Boolean expression is degenerated while logical equivalence is maintained, and the presence/absence of possibility that the penetrating conditions are fulfilled is determined. The penetrating condition functions are extracted so as to be divided into a GND side Boolean expression and a PWR side Boolean expression with a target net as a reference, and the presence/absence of a fear that stationary penetration current is generated is determined on the basis of whether or not the penetrating condition determination Boolean expression outputs a state that both the GND side Boolean expression and PWR side Boolean expression are simultaneously turned on. |
